Re: Superstitious learning in Computer Architecture ... Without a LOT of logic or some other better approach, re-executing the instructions requires re-decoding and it ties up the cache memory bus transferring more data as instructions than the instructions are working on. ... There is most of an order of magnitude in speed sacrificed by even HAVING a cache in a single ALU system, and more than an order of magnitude in multiple-ALU systems! ... (comp.arch.arithmetic)
Re: Iyonix instruction timings and RAM speed results ... I get 166/127 for main RAM and 5.7/62 for PCI Video memory on my original ...unrolled LDM/STM instructions for these, ... "add floating point" instruction takes almost 200 clock cycles,...MOV R0,R0,LSL #1 ... (comp.sys.acorn.misc)
PART 3. Why it seems difficult to make an OOO VAX competitive (really long) ... implementations, compared to high-performance RISCs, but also to IA-32.... "The VAX is so tied to microcode we predict it will be impossible to ... most frequently-used instructions can be converted to a small number ... given the increasing relative latency to memory.... (comp.arch)
Re: Cost of calling a standard library function ... > sense, since push Allocates memory, and pop deallocates it. ... Hence, all the CPU does is, basically: ... so forth...it's even possible to get "free" instructions (effectively ... what else is an ASM coder's job? ... (alt.lang.asm)
Re: [SLE] For or against ..Hyperthreading. ... > Let's say for mail or Database server...... Opteron and Athlon-64 also have a different memory access archetecture so ... - 64-bit Address registers means more memory is directly addressable, ... do a wider range of operations as primitive instructions (for example, fetch, ... (SuSE)
