Re: [PATCH] Mantaining turnstile aligned to 128 bytes in i386 CPUs

On Tuesday 25 July 2006 11:14, Attilio Rao wrote:
2006/7/25, Attilio Rao <attilio@xxxxxxxxxxx>:
Hi,
Intel documentation points out that having a 128-bytes aligned
syncronizing primitive (which fits in a cache line) will minimize the
traffic for cache bus, so this patch implements an alignment for i386
on turnstiles.

Any comments, feedbacks?

Oh, sorry, I've unforgotten the diff.

Attilio

I think a better approach would be to stick turnstiles (and sleepqueues) in a
UMA zone and specify cache-size alignment to the zone. However, turnstiles
aren't really sychronization primitives in that you don't spin on a variable
inside the structure, and I think it's the spinning and avoiding bouncing
cache lines around that Intel's documentation is really about. In that case,
the things you want aligned are things like mutexes, rwlocks, etc.

--
John Baldwin
_______________________________________________
freebsd-arch@xxxxxxxxxxx mailing list
http://lists.freebsd.org/mailman/listinfo/freebsd-arch
To unsubscribe, send any mail to "freebsd-arch-unsubscribe@xxxxxxxxxxx"

Relevant Pages

  • Re: [PATCH] Mantaining turnstile aligned to 128 bytes in i386 CPUs
    ... >> Intel documentation points out that having a 128-bytes aligned ... >> syncronizing primitive (which fits in a cache line) will minimize the ... >> on turnstiles. ... aren't really sychronization primitives in that you don't spin on a variable ...
    (freebsd-arch)
  • Re: [PATCH] Mantaining turnstile aligned to 128 bytes in i386 CPUs
    ... 2006/7/25, Attilio Rao: ... Intel documentation points out that having a 128-bytes aligned ... syncronizing primitive (which fits in a cache line) will minimize the ...
    (freebsd-arch)
  • Re: Xeon and Events
    ... NetBurst does not implement a traditional L1 instruction cache. ... when the Intel documentation mentions "the number of retired µops ...
    (comp.lang.asm.x86)