Re: Architectures with strict alignment?
- From: Erik Trulsson <ertr1013@xxxxxxxxxxxxx>
- Date: Sat, 29 Dec 2007 13:41:21 +0100
On Sat, Dec 29, 2007 at 06:03:15PM +0800, Erich Dollansky wrote:
Hi,
Kip Macy wrote:
Isn't it everything except x86?
not really.
All RISC based designs need the alignment so that the CPU can fetch a CPU
word in one go. CISC based designs do not have this limitiation.
I also do not know of any other CISC based design which made it to
mainstream.
Not quite true. Take for example the venerable Motorola 68000 CPU (used in
many different computers in the early and mid 80's).
It required all 16-bit (and 32-bit) accesses to be aligned on a 16-bit
boundary. This was later relaxed in the M68020 and later CPUs.
The M68k series is one of the classic CISC architectures and most certainly
made it to the mainstream.
(Admittedly FreeBSD does not support the M68k series. NetBSD and (older
releases of) OpenBSD does, but they require at least an 68020 - which does
not have strict alignment requirements.)
Erich
-Kip
On Dec 29, 2007 12:11 AM, Erich Dollansky <oceanare@xxxxxxxxxxxxxx> wrote:
Hi,
Ivan Voras wrote:
Hi,isn't this the case with SPARC and Itanium?
Which of the architectures FreeBSD supports (if any) have strict memory
alignment requirements? (in the sense that accessing a 32-bit integer
not aligned on a 32-bit address results in a hardware trap/exception).
I know, they are 64 bits.
Erich
--
<Insert your favourite quote here.>
Erik Trulsson
ertr1013@xxxxxxxxxxxxx
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- Re: Architectures with strict alignment?
... All RISC based designs need the alignment so that the CPU can fetch a CPU
word in one go. ... I also do not know of any other CISC based design which made it
to mainstream. ... (freebsd-hackers) - Re: [PATCH] Mantaining turnstile aligned to 128 bytes in i386 CPUs
... raw memory bandwidth is governed by RAS cycles. ... This means that the
more data you can load into the cpu on the 'read' ... Alignment is critical. ...
(freebsd-current) - Re: [PATCH] Mantaining turnstile aligned to 128 bytes in i386 CPUs
... raw memory bandwidth is governed by RAS cycles. ... This means that the
more data you can load into the cpu on the 'read' ... Alignment is critical. ...
(freebsd-arch) - Re: Flash Player for FC3 64 bit
... > same speed 32bit CPU. ... It ain't necessarily true. ...
or on a 64 bit OS, and (with the AMD designs) this is more or less true. ... Now some of
these libraries will probably ... (Fedora) - Re: WWDC -- MacBook Pro?
... But then alignment problems could cause a slowdown. ... Even the Alpha (Digital's
64 bit CPU that had ... Also the CPUs mostly talk to the L1 cache. ... main
memory. ... (comp.sys.mac.system)