Re: Architectures with strict alignment?



On Mon, Dec 31, 2007 at 05:38:43PM +0800, Erich Dollansky wrote:
Hi,

Kostik Belousov wrote:
On Sat, Dec 29, 2007 at 01:12:04PM +0200, Kostik Belousov wrote:
On Sat, Dec 29, 2007 at 12:14:11AM -0800, Kip Macy wrote:

I.e., it seems that gcc does not feel too guilty generating unaligned
half-word writes on i386. :(

this should not be a problem inside a cache line.

If the access goes accross two cache lines and the other cache line is
not in the cache, it becomes real difficult.

I can't tell you what the hardware actually does in this case.

It should read the second affected cache line into the cache. But what
happens if the second affected cache line is blocked by another CPU
while the current CPU blocks the first cache line?

From the manual, 253668, 7.1.1:

Accesses to cacheable memory that are split across bus widths, cache
lines, and page boundaries are not guaranteed to be atomic by the Intel
Core 2 Duo, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, P6 family,
Pentium, and Intel486 processors. The Intel Core 2 Duo, Intel Core Duo,
Pentium M, Pentium 4, Intel Xeon, and P6 family processors provide bus
control signals that permit external memory subsystems to make split
accesses atomic; however, nonaligned data accesses will seriously impact
the performance of the processor and should be avoided.

I think we might get any half of the operation as a result.

Attachment: pgpWM0fJD5wtO.pgp
Description: PGP signature



Relevant Pages

  • Re: cvs commit: src/sys/amd64/amd64 mp_machdep.c src/sys/i386/i386 mp_machdep.c
    ... caches are dangerous" to "a shared L1 data cache is dangerous". ... caches turns Intel Core Duo processors into Intel Core Solo processors. ... I do not pretend to understand the background, but from your description it sounds like performance on Core Duo machines will be bad unless this change is made, or the potentially dangerous sysctl is active. ...
    (FreeBSD-Security)
  • Re: Larrabee details: Yes, it is based on the Pentium. :-)
    ... The Pentium, like the IBM 360/195, combined the two performance- ... The 486 had about the same pipeline depth and also cache. ... Intel's Haifa team seems to be more successful than the ...
    (comp.arch)
  • Re: Pentium vs Celeron
    ... >half the cache. ... Celeron processor than the usual shoe-scrapings plus "Pentium Tax". ... 128k full-speed L2 cache, 400MHz base, SIMD ...
    (microsoft.public.windowsxp.general)
  • Re: Need cache chips for 1995-vintage PC
    ... The Pentium OverDrive and the 233MHz Pentium MMX represent the ... levels of cache into the Socket 7 K6-3, which will not run in the Advanced/MN ... a 200MHz Pentium Pro CPUs ...
    (comp.sys.hp.hardware)
  • Re: Re: How does an 800Mhz celeron compare to lower speed Pentium II
    ... > cache as a P-II ... > The 370 socket Pentium 3?s had twice the cache and for it?s time was ... > eat for dinner a similar speed 370 socket Pentium 3 chip. ... > socket processors started appearing with the faster clock speeds ...
    (alt.comp.hardware.pc-homebuilt)