Re: tunning disk cache for pgsql?



On Dec 28, 2010, at 7:59 AM, Nicolas Haller wrote:
I use a new box with 4GB RAM as a pgsql server. In pgsql, you can
set the effective_cache_size to indicate the memory available to cache
disk I/O.
As "recommended", my box use 1300MB to shared buffers (IPC shared memory)
and 2700 Mo to disk cache.

That's probably not a great mix unless your workload is very read-heavy. Writes will push data through shared buffers back into the OS, which will also try to cache it, so you'll end up with double-buffering.

If I look memory usage in top, it say:
Mem: 1154M Active, 1911M Inact, 601M Wired, 112M Cache, 417M Buf, 148M Free

The Cache reported by top in FreeBSD isn't filesystem cache; it's a cache for some internal stuff. Buf are filesystem buffers, but they're not the only mechanism for the OS to cache data. Most data is actually cached via active and inactive pages.
--
Jim C. Nasby, Database Architect jim@xxxxxxxxx
512.569.9461 (cell) http://jim.nasby.net


_______________________________________________
freebsd-performance@xxxxxxxxxxx mailing list
http://lists.freebsd.org/mailman/listinfo/freebsd-performance
To unsubscribe, send any mail to "freebsd-performance-unsubscribe@xxxxxxxxxxx"



Relevant Pages

  • Re: Cached memory never gets released
    ... Stock linux 2.4.26 kernel. ... Due to flash bug 3M of memory gets lost due to font memory getting lost ... The output of "free" cache number steadily grows. ... longer to exhaust all of system memory with the cache. ...
    (Linux-Kernel)
  • Re: Problem: Creating a raw binary string
    ... > While its true that a 64-bit cpu will move twice the data per instruction it ... > Memory bus width plays an important role here and unless it too is widened / ... You are forgetting the two levels of cache in the processor. ... The memory chips are addressed in Row col fashion. ...
    (alt.comp.lang.borland-delphi)
  • Re: Is Greenspun enough?
    ... Most OSes memory map executables directly from the file system so code doesn't pollute the file cache or swap space. ...
    (comp.lang.lisp)
  • Re: High-bandwidth computing interest group
    ... sequential access patterns, brute force - neither of us consider that interesting ... Perhaps we should lose the cache line orientation - transferring data bytes that aren't needed. ... Particularly if it has scatter/gather vector instructions like Larrabee, or if it is a CIMT coherent threaded architecture like the GPUs. ... As I have discussed in this newsgroup before, this allows us to have writeback caches where multiple processors can write to the same memory location simultaneously. ...
    (comp.arch)
  • Re: Superstitious learning in Computer Architecture
    ... Without a LOT of logic or some other better approach, re-executing the instructions requires re-decoding and it ties up the cache memory bus transferring more data as instructions than the instructions are working on. ... The concept of cache is fundamentally flawed in that it STILL restricts access to one word per clock cycle, when a single modern ALU can easily use 5 plus whatever is eaten up with instruction accesses. ... The size of an optimizing compiler is proportional to the SQUARE of the size of the language times the SQUARE of the complexity of the machine - because all interactions must be considered. ...
    (comp.arch.arithmetic)