Re: New itaniums out at 2.5x perform gain

In article <44c0b117$0$4147$9a6e19ea@xxxxxxxxxxxxxxxxxxxx>, Neil Rieck <n.rieck@xxxxxxxxxxxx> wrote:
and now 64 bit machine. In the process, it has gained many more
features. So while the 8086 circa 1990 was definitely ill suited to run
VMS, the CPUs made today for that architecture have gained respectability.

Despite what Intel + AMD marketing folks would have us believe, these
product lines you are referring to are not 64-bit. It may seem so, to some,
because CPU and "memory management" functions have been integrated (read
blurred) but these CPUs are only 32 bits wide.

Er... no, the latest 64-bit processors in that family _are_ true 64 bit
processors. I'll explain in a moment, if you'll bear with me, please. :)

To understand this better, think about the PDP-11 system which was a 16 bit
CPU. The memory management system allowed the CPU to address memory using
18-bit, 22-bit, and 24-bit access. This worked by having the CPU first
initialize MMU registers which were later combined (added) with 16-bit
addresses coming from the CPU to generate a wider address going to memory.
But there was "no way" any single process could "see" more than 16-bits of
memory at a time without first asking the OS to manipulate the associated
memory management registers.

Right: the PDP-11 had a 16-bit data bus and 16 to 22 bit address bus
depending on what memory access scheme was being used.

The data bus width is why the PDP-11 is considered to be a 16 bit
processor.

Same deal with the 65816 which was used in the Apple IIGS and Super
Nintendo systems: 16-bit data bus, 24-bit address bus, considered to be
a 16-bit processor.

However, the EM64T and AMD64 processors *are* full 64 bit internally.

They are at least 64 bits wide for the _data_ bus (as well as for the
various registers including all of the GPRs), which is the big thing.

All pointers are 64-bit. All pushes and pops for the stack is 64-bit.
(The operands are 32-bit wide, but then again, do they really need more
than ~4.2 billion defined operands?)

Accessing data in the registers and memory is not a matter of internally
stringing up two adjacent 32-bit registers or 32-bit memory addresses.
(First version of this stuff may have done that, but current versions
don't. It's a full and true 64-bit access.)

The address bus is not quite 64-bit wide in current implementations, but
likely eventually will either reach 64-bit or come closer to it --
today's implementations are still much wider than terrible 32-bit hacks
like PAE to squeeze an extra 4 bits out of addressing.

On AMD64 64-bit processors, 32-bit is available as a _compatibility mode_.
I'm not sure if it's considered to be a compat mode on EM64T.

For more detailed information about these two architectures:

http://en.wikipedia.org/wiki/AMD64
http://en.wikipedia.org/wiki/EM64T

(The EM64T page is rather sparse, admittedly. AMD64 page is pretty good.)

One of the big things distinguishing EM64T and AMD64 from other
traditional 64-bit implementations such as Alpha, UltraSPARC, POWER3
(and later), Itanium, etc. is that EM64T/AMD64 has *much* fewer GPRs due
to their precedessors originally being a CISC design.

Cheers,

-Dan
.

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