Intel to add new instructions to 8086

from:
http://news.com.com/Intel+to+extend+x86+for+new+tasks/2100-1006_3-6120335.html?tag=nefd.top

##
The new instructions are scheduled to debut in the "Penryn" generation
of processors, due to start arriving in 2008 and built using a
manufacturing process with 45-nanometer features,
<...>
The instructions fall into two broad categories. First is SSE4, the
fourth generation of Streaming SIMD (single instruction, multiple data)
Extensions. SIMD lets a chip take the same action with more than one
data element, instead of requiring an instruction to be paired with each
element--an approach that economizes many operations dealing with
graphics, video and audio. SSE4 also will improve high-performance
computing, Intel said.

The second category accelerates two specific applications. One is
searching and pattern-matching, useful for tasks such as handwriting
recognition and genetic research. The other is cyclical redundancy check
(CRC) technology, which monitors the integrity of data transfer to and
from storage systems and other computers.

##


Question: is it my imagination or is Intel moving in the exact opposite
direction of RISC by adding fairly complex instructions ?


Let say, for the sake of my question, that VMS was already running on
that architecture. Is there much work involved in making VMS run on the
new version of the chip that supports new instructions ? For instance,
it is very cumbersome to have a version of VMS run on both a version of
the chip that doesn't have the instruction and a version of the chip
that does ?

Or would it just mandate that starting with version X, you must have
generation Y of the chip with support for those instructions ?

or would VMS simply not be changed but allow the standard compilers to
generate binary code that uses those instructions?
.

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