Re: Pc audio card for Itaniums


When X11 was first done, the keyboard at the time (the LK201/401) had a
"bell" and a keyclick. You could set the volume of each and turn them off.
The bell was just a simple command to the KB.

The PS2 keyboard had no sound capability. But the junk IO has a square wave
generator. So you turn on the tone, and then turn it off. There is no
volume.

When DW was written, the bell was in the KB so it was a SETMODE QIO to the
keyboard driver. When it moved to the junk IO, I hacked it into the KB
driver. When EV7 came out I added a external method to implement sound -
but we never had a demand for it and it was never used. We have a customer
who needs it on Integrity - so we have implemented that external method to
call the *limited* functionality sound driver.


Essentially to turn on the bell, first you need to walk the ADP's and find
the base of ISA space - there are IOC$ routines that you can use to
implement the read/write byte code. But for a system with dense space, you
just add the offset to the mapped base and do a unsigned byte operation.
Make sure to define the address as volatile.


#define TIMER_INTERVAL 0x42
#define TIMER_CTL 0x43
#define NMI_STATUS 0x61

#define _set_NMI_STATUS( v) { \
int d; \
d = _read_io_byte(NMI_STATUS); \
_write_io_byte(NMI_STATUS, d | v); \
}

#define _clear_NMI_STATUS( v) { \
int d; \
d = _read_io_byte(NMI_STATUS); \
_write_io_byte(NMI_STATUS, d & ~v); \
}

/*
* Turn on gate and speaker data for counter 2.
* NMI Status Register:
* GATE set (enable Ctr 2) - bit 0
* SPKR set (AND w/ Ctr 2) - bit 1
*/
_set_NMI_STATUS( 0x03);

/*
* Set Counter 2 to "pitch".
* Timer 1 Control reg (timer_ctl):
* OUT pin is 1 - bit 7
* Counter Latch LSB then MSB - bits 4 & 5
* Mode 3 (Square Wave Mode) - bits 1 & 2
* Timer 1 Counter 2 (timer_interval): LSB
* Timer 1 Counter 2 (timer_interval): MSB
*/
_write_io_byte(TIMER_CTL, 0xb6);
_write_io_byte(TIMER_INTERVAL, pitch&0xff);
_write_io_byte(TIMER_INTERVAL, (pitch>>8)&0xff);

To turn it off:

/*
* Turn off gate and speaker data for counter 2.
* NMI Status Register:
* GATE clear (disable Ctr 2) - bit 0
* SPKR clear (AND w/ Ctr 2) - bit 1
*/
_clear_NMI_STATUS( 0x03);

/*
* Reset Counter 2 to zeros
* Timer 1 Control reg (timer_ctl):
* OUT pin is 1 - bit 7
* Counter Latch LSB then MSB - bits 4 & 5
* Mode 3 (Square Wave Mode) - bits 1 & 2
* Timer 1 Counter 2 (timer_interval): LSB
* Timer 1 Counter 2 (timer_interval): MSB
*/
_write_io_byte(TIMER_CTL, 0xb2);
_write_io_byte(TIMER_INTERVAL, 0x00);
_write_io_byte(TIMER_INTERVAL, 0x00);



"JF Mezei" <jfmezei.spamnot@xxxxxxxxxxxxx> wrote in message
news:008b4740$0$11623$c3e8da3@xxxxxxxxxxxxxxxxxxxx
FredK wrote:
Find any generic documentation on the "junk IO" chip for any antique IBM
PC.
There is a square wave generator in ISA space. It it exactly the same
junk
IO chip in exactly the same place in ISA space as a PC. Walk the ADP list
until you find the ISA ADP and in the ADP you will find the base SVA of
where it (ISA space) is mapped. On a DS10 you don't need to do anything
fancy to talk to it (no sparse space for example).

Thanks. That is a lot to learn for me. But I did find some code with Mr
Google that walks "ADP" (I assume this is for adaptors ?) to find the
ISA (I have no idea what that is, is this IDE stuff ?)

Out of curiousity, how does decwindows generate the beeps ? Does it have
platform specific code ?

I assume it is quite different between for instance a vaxstation that
has the piezo sound generated by the keyboard, or an alphs like the
DS10 with primitive sound, or an alpha with a real sound card ?

Doesn't VMS provide an abstraction layer to simplify decwidnows' life
when it come to generating a beep ?


.

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