Re: Cache line size for L1, L2, L3

Alex Vinokur wrote:
Hi,

Here is output of utility machinfo.


<machinfo output snipped>

I have two questions related to Cache info.
1. What is 'associativity' in the row
L1 Instruction: size = 16 KB, associativity = 4

In this case, I think http://en.wikipedia.org/wiki/CPU_cache might
be faster than trying to recreate that summary. It isn't a bad
overview.


2. How can we know what is cache line size (length) for L1, L2, L3?

That's a harder trick. From what I can tell your options are:

1) Figure out some fairly arcane firmware calls and have the
privilege to use them [not likely]

2) Use your family, model and revision to look it up with
Intel. (From http://www.intel.com/products/processor/itanium/specifications.htm?iid=Itanium+tab_specifications
this has to be the 9110N since you show 1.60GHz clock on 400MHz FSB
and 12Mb of L3). Unfortunately, no amount of searching tells me exactly
what cache line sizes that uses (there's a processor specifications tool
linked at the bottom of the page, but it doesn't list this model or any
of the 9100 series, oddly enough).

3) Upgrade to 11iv3 and just do machinfo -v -v (or try to figure out the
pstat_getprocessor() output). Sorry, but that information simply isn't
there in v2 interfaces. [The kernel knows, but I never recommend folks
going and trying to read kernel variables that aren't documented...
one patch and your application can easily stop working].

Are you planning on implementing your own spinlocks? Otherwise, I'm
curious as to why this matters. I can say from experience that your
line sizes are going to be either 64 or 128 bytes -- that's been true
on all the IPF processors I've encountered (older ones were 64, newer
ones tend to be 128). But I can't call that a documented/verified fact.

Don
--
kernel, n:
A part of an operating system that preserves the medieval traditions
of sorcery and black art.
.

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