Re: ultra 60 not booting

From: Niall Dalton (niall_at_xrnd.com)
Date: 11/23/04 

Date: Tue, 23 Nov 2004 15:45:31 +0000

> You mean that your entire world does not revolve around your U60?!?
> Shame on you ;-)

Indeed - in my defense I am but a humble programmer rather than an
administrator. Ok, a systems programmer, so perhaps not that humble ;-)

> Err... does your U60 have a second frame buffer? ie. Do you have both
> 13W3 and VGA-style video outputs? If yes, then which are you using? If
> its the VGA-style one, then toss it and buy a 13W3 to VGA convertor.
> eBay is your friend, but make sure you get the correct gender-ed convertor.

It has just the one, and I was using a 31w3 to vga convertor.

> Then power on again, and hopefully POST will run. If you can snap the
> serial output to a file and post any POST errors here if they occur
> (hopefully not).

Picked up the cable earlier, and managed to get POST to run. Doesn't
look pretty. RAM errors and scsi devices not showing up...

Thanks for the help on this!

Hardware Power ONk #2 0 0 0
Master CPU onlinesTTnnPPCC==000000
Master Version: 0000.0000.1700.11a0

Probing Memory Bank #3 0 0
Slave Version: 0000.0000.1700.11a099ee88 TTSSTTAATTEE==00000000..000
CPU E$ (M) 0000.0000.0040.0000 (S) 0000.0000.0040.0000ÿ
0> <00> SC Reg Index Test

TTLL==00
Button Power ON..00000000..000
Master CPU online000..00000000..00
Master Version: 0000.0000.1700.11a000000000..00000055 TTTT==00000000.
Slave Version: 0000.0000.1700.11a0

       TTPPCC==00000000..00000000.
CPU E$ (M) 0000.0000.0040.0000 (S)
0000.0000.0040.0000000000..0000000000..00000000..eeffffff..ff99ee44 TTnn

Probing keyboard Doneeeffffff..ee333388 T
%o0 = 0000.0000.0000.200104444..55660044..11440000

Executing Power On SelfTest8 TTSSTTAATTEE==00000000..

0>44
0>@(#) Sun Ultra 60(UltraSPARC-II 2-way) UPA/PCI POST 2.0.2 10/19/1998
10:46 AM000000..0000000000..00000000..00000000000000..00000000..00000044
  TTTT==0000000
0>INFO: Processor 0 is master.USPECT=

0>
0> <00> Probe Ecache00..00000000..000000
0>INFO: CPU 450 MHz: 4096KB Ecache00000000..00000000..eeffffff..ee77
0> <00> Ecache RAM Addr Test000PP

       TTPPCC==0000000
0> <00> Ecache Tag Addr Test44 TTnnPPCC==00000000..0000
0> <00> Ecache Tag TestTSSTTAATTEE==00000000..
0> <00> Invalidate Ecache Tags.556
00..eeffffff..ff99ee88 T
0>INFO: Processor 2 - UltraSPARC-II.0044..11440000EEDD SSttaattee EExx
0> <00> Init SC RegsT==00000000..0000000
0> <00> SC Address Reg Test0..00000000..00000000..0000
0> <00> SC Reg Index TestInt to mid
..00006644
0> <00> SC Regs Te
0> <00> Probe Memory0004444..55660044..1
0>INFO: 512MB Bank 0
0>INFO: 512MB Bank 1

RREEDD SSttaat
0>INFO: 0MB Bank 2000000..00000000..00
0>INFO: 0MB Bank 30..00000000..0000000
0> <00> Malloc Post Memory TTTT==00000000..00000000
0> <00> Init Post Memory00

..00006644CC==000000
0> <00> Post Memory Addr Test0000..eeffffff..ff99ee44 TTn
0> <00> Map PROM/STACK/NVRAM in DMMU..eeffffff..ff99ee44 TTnnPPCC==0000
0> <00> Memory Stack Test7668
00..eeffffff..ff99ee
2> <00> DMMU TLB Tag Access Test444..55660044..11440000ff99ee88
2> <00> DMMU TLB RAM Access Test..55660044..11440000EEDD SSttaa
2> <00> IMMU TLB Tag Access Test00000..00000022 TTTT==00000000.
2> <00> IMMU TLB RAM Access Test00..00000044 TTTT==00000000..00
2> <00> Probe Ecache44.00

..0000
0> <00> DMMU Little Endian Test00PPCC==00000000..0000000000..0
0> <00> IU ASI Access Test TTnnPPCC==00000000..00
0
0> <00> FPU ASI Access TestTAATTEE==00000000..00004444
2> <00> DMMU Hit/Miss Test60044..11440000ff99ee88 T
2> <00> IMMU Hit/Miss Test4444..55660044..

RREE
2> <00> DMMU Little Endian Testnn11 TTTT==00000000..00000000.
2> <00> IU ASI Access Test..00000000..00000000..0000
2> <00> FPU ASI Access Test
..00006644= 0000.0
2> <00> Dcache R
0> <1f> PIO Read Error, Target Abort Test00000000000..00000000..00000055
  TTTT==00
0> <1f> PIO Write Error, Master Abort Test

..00006644CC==000000

       TTPPCC==0000
0> <1f> PIO Write Error, Target Abort
TestC==00000000..0000000000..00000000..eefffff
0> <1f> Timer Increment Test00..000000.eeffffff..ee77668
0> <00> Copy Post to MemorySTTAATTEE==00000000..000044
0> <00> Ecache Thrash Teste88 TTSSTTAATTEE==0000000
0> <00> Init Memory4..11440000EEDD SS
0> <00> Memory Addr w/ Ecache Test0000000..00000033 TTTT==00000000.
0>INFO: 512MB Bank 00000..00000000..0000
0>INFO: 512MB Bank 1.00
..00
0>INFO: 0MB Bank 20006644

0>INFO: 0MB Bank 200000000..00000055
0>INFO: 0MB Bank 3000..0000
..00006644
0> <00> Memory Status Test0000000..00000000..eefffff
0>INFO: 512MB Bank 0==00000000..000000PP
0>INFO: 512MB Bank 1000..00000000..eefff
0>INFO: 0MB Bank 2CC==00000000..00
00.
0>INFO: 0MB Bank 3TTSSTTAATTEE==000000
0> <00> V9 Instruction Test000044..55660044..11440000f
0> <00> CPU Tick and Tick Compare Reg Test55660044..

TTLL==00000000..00000000..0000
0> <00> CPU Soft Trap Test000..00000000..0000000000.
0> <00> CPU Softint Reg and Int Test00000044 TTTT==00000000..00
2> <00> V9 Instruction Test

RREEDD SSttaattee E
0> <1f> PIO Decoder and BCT Test00..00000000..00000000

TTLL==
0> <1f> PCI Byte Enable Test.00000055 TTTT==00000000..0
0> <1f> Counter/Timer Limit Regs Test TTPPCC==00000000..00000000..eefff
0> <1f> Timer Reload Test0006644..000000PP

0> <1f> Timer Periodic Testeeffffff..ff99ee44 TTnnPPC
0> <1f> Mondo Int Map (short) Reg Test TTSSTTAATTEE==00000000..00004444..556
0> <1f> Mondo Int Set/Clr Reg Test..ff99ee88 TTSSTTAATTEE==00000000
0> <1f> Psycho IOMMU Regs TestEDD SSttaattee EExxcceepptti
0> <1f> Psycho IOMMU RAM Address Test00000

TTLL==00000000..00000000..00
0> <1f> Psycho IOMMU CAM Address Test
..00006644

0> <00> Test 0: prefetch_mr00000..0000000000..00000000
0> <00> Test 1: prefetch to non-cacheable page00000..00000000..0000
..00006644

0> <00> Test 2: prefetch to page with dmmu misss4
TTnnPPCC==00000000..000000PPCC==00000000..000
0> <00> Test 3: prefetch miss does not check alignment00..00
00..eeffffff..ee776688 TTSSTTAATTEE==00000000.
0> <00> Test 4: prefetcha with asi 0x4c is noped00ff99ee88
TTSSTTAATTEE==00000000..00004444..55
0> <00> Test 5: prefetcha with asi 0x54 is nopedonn11
TTTT==00000000..00000000..00000000

TTL
0> <00> Test 6: prefetcha with asi 0x6e is noped00000000..00
..00006644

0> <00> Test 20: prefetcha10_6: illegal instruction
trapnnPPCC==00000000..000000PPCC==00000000..000000
0> <00> Test 21: prefetcha11_1w
00..eeffffff..
0> <00> Test 22: prefetcha81_31..00004444..55660044..114400004
0> <00> Test 23: prefetcha11_15: illegal instruction trap

TTLL==00000000..00000000..00000000..00
2> <00> UltraSPARC-2 Prefetch Instructions
Test000000..00000000000000..00000000..00000055 TTT
2> <00> Test 0: prefetch_mr..00006644

2> <00> Test 1: prefetch to non-cacheable page
TTnnPPCC==00000000..000000PPCC==00000000..00
2> <00> Test 2: prefetch to page with dmmu misss=00000000..00
00..eeffffff..ee333388 TTSSTTAATT
2> <00> Test 3: prefetch miss does not check alignment.11440000ff99ee88
  TTSSTTAATTEE==00000000..00004444..5
2> <00> Test 4: prefetcha with asi 0x4c is noped000011
TTTT==00000000..00000000..0000000000..00
2> <00> Test 5: prefetcha with asi 0x54 is noped=00000000..00
..00006644

RREEDD SSttaatt
2> <00> Test 10: prefetch with fcn 1200..00000000..00000000

TTLL==00000
2> <00> Test 11: prefetch with fcn 16 is noped00..00000000..000000000006644

2> <00> Test 12: prefetch with fcn 29 is noped TTnnPPC
..00006644..000000PP

       TTPPCC==
Master CPU online
Master Version: 0000.0000.1700.11a0
Slave Version: 0000.0000.1700.11a0
CPU E$ (M) 0000.0000.0040.0000 (S) 0000.0000.0040.0000

@(#) UPA/PCI 3.23 Version 1 created 1999/07/16 12:08
Clearing DTAGS Done
Probing Memory Done
MEM BASE = 0000.0000.2000.0000
MEM SIZE = 0000.0000.2000.0000
MMUs ON
Copy Done
PC = 0000.01ff.f000.2800
PC = 0000.0000.0000.2844
Decompressing into Memory Done
Size = 0000.0000.0006.eb80
ttya initialized
SC Control: EWP:0 IAP:0 FATAL:0 WAKEUP:0 BXIR:0 BPOR:0 SXIR:0 SPOR:1 POR:0
Probing Memory Bank #0 128 128 128 128 : 512 Megabytes
Probing Memory Bank #1 128 128 128 128 : 512 Megabytes
Probing Memory Bank #2 0 0 0 0 : 0 Megabytes
Probing Memory Bank #3 0 0 0 0 : 0 Megabytes
Data Access Error
ok probe-scsi
ok probe-scsi-all
ok boot
Boot device: net File and args:

Can't open boot device

ok