Re: chip multithreading on ultrasparc iv

From: David Kanter (dkanter_at_gmail.com)
Date: 10/27/04 

Date: 27 Oct 2004 13:21:13 -0700

Rich Teer <rich.teer@rite-group.com> wrote in message news:<Pine.SOL.4.58.0410221129030.17681@zaphod.rite-group.com>...
> On Fri, 22 Oct 2004, tri wrote:
>
> > The Ultrasparc IV has 2 Ultrasparc III pipeline cores capable of
> > executing instructions from a separate thread on each core.
> >
> > Does this mean in one clock cycle, instructions from 2 threads can
> > execute on the Ultrasparc IV processor?
>
> Yes. Niagra will be able to execute 32 threads simultaneously.

Each core can simultaneously exec. instructions from a single. So
with two cores, each US-IV device can execute instructions from 2
different threads simultaneously.

Niagara does not execute 32 threads simultaneously. Niagara uses
Switch on Event MultiThreading also known as SoEMT or CMT (Coarse
Multithreading). This is similar to Intel's Montecito, except that
Montecito hosts 2 threads per core, whereas Niagara hosts 4.

Only one thread can use the core at a time, so a Niagara device, with
8 cores, can only execute instructions from 8 different threads at
once.

I suspect you were thinking about what would happen if each Niagara
core used SMT rather than CMT.
 
> > Does the Ultrasparc IV also maintain architectural states for each
> > thread?
>
> Not sure what you're asking here...

There is one thread for each core in the US-IV, so of course it does.
US-IV is exactly like a 2P system on a single chip.

David Kanter
Editor
Real World Technologies

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