Make: Variables expansion in recursive make

From: Fabrice Gautier (droopycom_at_yahoo.com)
Date: 01/22/04 

Date: 22 Jan 2004 04:07:12 -0800

Hi,

I have some trouble understanding how make expand variables when
passing trhough the environment (recursive make case).
Here is my situation:

  I have a first makefile that declares a INCLUDE variable

$(INCLUDES)= -I$(@D)
export INCLUDES

  and a target that calls a recursive make like this

libgcc: some_deps
    echo $@ --- $(@D) --- $(INCLUDES)
    $(MAKE) MAKEOVERRIDES= -f libgcc.mk

  The second makefile (libgcc.mk) have some targets like this:

libgcc/./_foo.o: some deps
    echo $@ --- $(@D) --- $(INCLUDES)
    $(GCC) $(INCLUDES) foo bar

So when running the first makefile, for the libgcc target, the echo
shows:
  echo libgcc --- . --- -I.
which is what I expect.

When running the second Makefile, the echo in the libgcc target shows:
  echo libgcc/./_foo.o --- libgcc/. --- -I

which will eventually make the build fail because -I is not a valid
flag for gcc.

I'm assuming that in this case the INCLUDES variable was expanded when
calling the second make. Am i correct here? If i am, then i dont
understand why include was received as "-I" instead of "-I." in the
second makefile.

I understand that $(@D) should expand to the directory part of the
target filename (ie $@). Some test showed that if $@ is of the form
"/filename" then the $(@D) will be empty. If theres no dir in $@ then
$(@D) is just ".". Otherwise its the directory name.

As you can imagine, this happens while compiling gcc, so this should
work in many case, but i'm trying to understand why not in this one
(which is cross compiling gcc for an arm-elf target on a mingw32 host)

Any suggestion?

Thanks

-- Fab.

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